Hi Speed DEMUX (Demultiplexer) Apr 10, 2006 • Rohit VHDL library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; entity hispeeddemux is port (inp: in std_logic_vector(3 downto 0); ch0, ch1, ch2: out std_logic_vector(3 downto 0); res, clk: in std_logic); end hispeeddemux; architecture beh_hispeeddemux of hispeeddemux is signal out_now:natural:=0; begin process (clk, res) begin if clk='1' and clk'event then if res ='1' then out_now<=0; ch0<="UUUU"; ch1<="UUUU"; ch2<="UUUU"; else case out_now is when 0 => ch0 <=inp; when 1 => ch1 <=inp; when 2 => ch2 <=inp; when others => null; end case; out_now <= (out_now+1) mod 3; end if; end if; end process; end beh_hispeeddemux; Testbench library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; entity hispeeddemux_tb is end hispeeddemux_tb; architecture beh_hispeeddemux of hispeeddemux_tb is component hispeeddemux port (inp :in std_logic_vector(3 downto 0); ch0, ch1, ch2: out std_logic_vector(3 downto 0); res, clk:in std_logic); end component; signal input, ch0, ch1, ch2: std_logic_vector(3 downto 0):="0000"; signal clkfast, res: std_logic:='0'; begin comp:hispeeddemux port map(input, ch0,ch1,ch2,res,clkfast); clkfast<=not clkfast after 50 ns; process begin input<="1000"; wait for 100 ns; input<="0100"; wait for 100 ns; input<="0101"; wait for 100 ns; input<="1001"; wait for 100 ns; res<='1'; wait for 400 ns; res<='0'; end process; end beh_hispeeddemux; Add reply Click here to reply to the blog post instead Send