Binary to Gray code converter

library ieee;
use ieee.std_logic_1164.all;

entity B2G is
port(i:in std_logic_vector(3 downto 0);
     o:out std_logic_vector(3 downto 0);
     e:in std_logic);
end B2G;

architecture DataFlow of B2G is
begin

o(0)<=((i(0)and (not i(1)))or((not i(0))and(i(1))))and e;
o(1)<=((i(2)and (not i(1)))or((not i(2))and(i(1))))and e;
o(2)<=((i(2)and (not i(3)))or((not i(2))and(i(3))))and e;
o(3)<=i(3)and e;

end DataFlow;

Testbench

library ieee;
use ieee.std_logic_1164.all;

entity B2GTB is
end B2GTB;

architecture BehavioralTB of B2GTB is

component B2G is
port(i:in std_logic_vector(3 downto 0);
     o:out std_logic_vector(3 downto 0);
     e:in std_logic);
end component;

signal i:std_logic_vector(3 downto 0);
signal o:std_logic_vector(3 downto 0);
signal e:std_logic;

begin

inst:B2G port map(i,o,e);

process

begin

e<=transport'1' ;
wait for 10 ns;

i<=transport "0000";
wait for 10 ns;

i<=transport "0010";
wait for 10 ns;

i<=transport "0110";
wait for 10 ns;

i<=transport "1000";
wait for 10 ns;

i<=transport
 "1001";
wait for 10 ns;

i<=transport "1111";
wait for 10 ns;

end process;
end BehavioralTB;