library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;

entity mod5 is
    port (inp, rst, clk: in bit; remainder: out natural);
end mod5;

architecture divider of mod5 is
    signal present:natural := 0;
    begin
    process (clk)
    begin
    if (clk='1' and clk'event) then
        if rst='1' then
            present <=0;
        else
            case present is
                when 0 =>
                    if inp = '0' then
                        present <=0;
                    elsif inp = '1' then
                        present <=1;
                    end if;
                when 1 =>
                    if inp = '0' then
                        present <=2;
                    elsif inp = '1' then
                        present <=3;
                    end if;
                when 2 =>
                    if inp = '0' then
                        present <=4;
                    elsif inp = '1' then
                        present <=0;
                    end if;
                when 3 =>
                    if inp = '0' then
                        present <=1;
                    elsif inp = '1' then
                        present <=2;
                    end if;
                when 4 =>
                    if inp = '0' then
                        present <=3;
                    elsif inp = '1' then
                        present <=4;
                    end if;
                when others =>
                    null;
                end case;
        end if;
    end if;
    end process;        
    remainder <=present;    
end divider;

Testbench

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;

entity mod5_tb is
end mod5_tb;

architecture arc_tb of mod5_tb is
    component mod5
        port (inp, rst, clk:in bit; remainder: out natural);
    end component;
    signal a, rst,c: bit :='0';
    signal r: natural;
    signal num:natural;
begin    
    div:mod5 port map(a,rst,c,r);
    c<= not c after 100 ns;
    process (c)
    begin
    if (num mod 3 = 0) then
        a <= '1';
    else
        a <= '0';
    end if;
    num <= num+1;
    end process;
end arc_tb;