Serial in parallel out shift register

library ieee;
use ieee.std_logic_1164.all;

entity SIPO is
port(Din:in std_logic;
     o:out std_logic_vector(3 downto 0);
     clk:in std_logic);
end SIPO;

architecture Behavioral of SIPO is

begin

process(clk)
variable temp:std_logic_vector(3 downto 0):="0000";

begin

    if(clk'event and clk='1') then
        temp(3):=temp(2);
        temp(2):=temp(1);
        temp(1):=temp(0);
        temp(0):=Din;
        o<=temp;
    end if;
    
end process;

end Behavioral;

Testbench

library ieee;
use ieee.std_logic_1164.all;

entity SIPOTB is
end SIPOTB;

architecture Behavioral of SIPOTB is
component SIPO is
port(Din:in std_logic;
     o:out std_logic_vector(3 downto 0);
     clk:in std_logic);
end component;

signal Din,clk:std_logic;
signal o:std_logic_vector(3 downto 0);

begin

inst:SIPO port map(Din,o,clk);

process

begin
    clk<=transport '1';
    Din<=transport '1';
    wait for 10 ns;
    clk<=transport '0';
    wait for 10 ns;
    
    clk<=transport '1';
    Din<=transport '0';
    wait for 10 ns;
    clk<=transport '0';
    wait for 10 ns;
    
    clk<=transport '1';
    Din<=transport '1';
    wait for 10 ns;
    clk<=transport '0';
    wait for 10 ns;
    
    clk<=transport '1';
    Din<=transport '0';
    wait for 10 ns;
    clk<=transport '0';
    wait for 10 ns;
    
end process;

end Behavioral;

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