Arithmetic Logic Unit (ALU)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ALU is
    Port ( A : in std_logic_vector(3 downto 0);
           B : in std_logic_vector(3 downto 0);
           sel : in std_logic_vector(2 downto 0);
       carry : out std_logic;
           o : out std_logic_vector(3 downto 0);
           en,rst:in std_logic);
end ALU;

architecture Behavioral of ALU is

begin
    process(sel)
    begin
       if rst='1' then
           o<="0000";
       elsif en='1' then
       case sel is 
           when "000"=> o<=A or B;  --- Logical OR

        when "001"=> o<=A and B; --- Logical AND

        when "010"=> o<=not(A);  --- Logical NOT

        when "011"=> o<=A xor B; --- Logical XOR

        when "100"=> o<=A+B;     --- Arithmetic + with carry

                   if((A+B)>"1111") then carry<='1';
                   else carry<='0';
                   end if;
        when "101"=> o<=A-B;     --- Arithmetic - with borrow

                   if(A<B) then carry<='1';
                   else carry<='0';
                   end if;
        when "110"=> o<=A+1;     --- Increment

                   if(A="1111") then carry<='1';
                   else carry<='0';
                   end if;
        when "111"=>  o<=A;     
        when others=> o<=A;
            carry<='0';
    end case;    
    end if;
end process;                        
end Behavioral;

Testbench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ALUTB is 
end ALUTB;

architecture Behavioral of ALUTB is

component ALU is
Port ( A : in std_logic_vector(3 downto 0);
           B : in std_logic_vector(3 downto 0);
           sel : in std_logic_vector(2 downto 0);
       carry : out std_logic;
           o : out std_logic_vector(3 downto 0);
           en,rst:in std_logic);
end component;

signal A,B,o:std_logic_vector(3 downto 0);
signal sel:std_logic_vector(2 downto 0);
signal carry,en,rst:std_logic;

begin

inst:ALU port map(A,B,sel,carry,o,en,rst);

process

begin

rst<=transport '1';
wait for 10 ns;

rst<=transport '0';
en<=transport '1';
wait for 10 ns;

A<=transport "0100";
B<=transport "0110";
sel<="000";
wait for 10 ns;

sel<="001";
wait for 10 ns;

sel<="010";
wait for 10 ns;

sel<="011";
wait for 10 ns;

sel<="100";
wait for 10 ns;

sel<="101";
wait for 10 ns;

sel<="110";
wait for 10 ns;

sel<="111";
wait for 10 ns;

end process;

end Behavioral;

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