library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity TLC is
port(clk,rst:in std_logic;
     Green,Red,Yellow:out std_logic;
     state:inout integer);
end TLC;

architecture Behavioral of TLC is
signal count:integer range 0 to 10:=0;

begin
process(clk,rst)
begin
    if(rst='1') then
        state<=0;
        Red<='1';
        Green<='0';
        Yellow<='0';
        count<=0;
    elsif clk'event and clk='1' then
    case state is
    when 0 =>    ---Red Light

        if(count=5) then
            count<=0;
            state<=1;
        else
            count<=count+1;
            Red<='1';
            Green<='0';
            Yellow<='0';
        end if;
    when 1 =>     ---Green Light

        if(count=5) then
            count<=0;
            state<=2;
        else
            count<=count+1;
            Red<='0';
            Green<='1';
            Yellow<='0';
        end if;    
    when 2 =>    ---Yellow light

        if(count=2) then
            count<=0;
            state<=0;
        else
            count<=count+1;
            Red<='0';
            Green<='0';
            Yellow<='1';
        end if;
    when others =>
        state<=0;
        count<=0;
    end case;
    end if;
end process;

end behavioral;

Testbench

library ieee;
use ieee.std_logic_1164.all;

entity TLCTB is
end TLCTB;

architecture Behavioral of TLCTB is

component TLC is
port(clk,rst:in std_logic;
     Green,Red,Yellow:out std_logic;
     state:inout integer);
end component;

signal clk,rst,Green,Red,Yellow:std_logic;
signal state : integer;

begin

inst:TLC port map(clk,rst,Green,Red,Yellow,state);
process
variable temp:std_logic:='0';
begin

rst<=transport '1';
wait for 10 ns;

rst<=transport '0';
wait for 10 ns;

clk<=transport temp;
wait for 10 ns;

for i in 1 to 100 loop
    temp:=not temp;
    clk<=transport  temp;
    wait for 10 ns;
end loop;

end process;

end Behavioral;