4 X 2 Encoder Apr 10, 2006 • Rohit VHDL library ieee ; use ieee.std_logic_1164.all ; entity encoder4x2 is port(i:in std_logic_vector(3 downto 0); o:out std_logic_vector(1 downto 0); e:in std_logic); end encoder4x2; architecture behavioral of encoder4x2 is signal temp:std_logic_vector(1 downto 0); begin process(i,e) begin temp<="ZZ"; if(e='1') then case i is when "0001"=> temp<="00"; when "0010"=> temp<="01"; when "0100"=> temp<="10"; when "1000"=> temp<="11"; when others=> temp<="ZZ"; end case; end if; o<=temp; end process; end behavioral; Testbench library ieee; use ieee.std_logic_1164.all; entity encoder4x2TB is end encoder4x2TB; architecture behavioral of encoder4x2TB is component encoder4x2 port(i:in std_logic_vector(3 downto 0); o:out std_logic_vector(1 downto 0); e:in std_logic); end component; signal i:std_logic_vector(3 downto 0); signal o:std_logic_vector(1 downto 0); signal e:std_logic; begin inst:encoder4x2 port map(i,o,e); process begin e <= '1' after 10 ns; i <= "0001" after 10 ns; i <= "0010" after 10 ns; i <= "0100" after 10 ns; i <= "1000" after 10 ns; end process; end behavioral; Add reply Click here to reply to the blog post instead Send