library ieee;
use ieee.std_logic_1164.all;

entity Decoder2x4 is
    port(i :in std_logic_vector(1 downto 0);
          e :in std_logic;
          o :out std_logic_vector(3 downto 0));
end Decoder2x4;

architecture Behavioral of Decoder2x4 is

begin 

process(i,e)

begin
    if(e='1') then
        o(0)<=(not i(0))and(not i(1));
        o(1)<=(i(0))and(not i(1));
        o(2)<=(not i(0))and(i(1));
        o(3)<=(i(0))and(i(1));
    else
        o<="ZZZZ";
    end if;

end process;

end Behavioral;

Testbench

library ieee;
use ieee.std_logic_1164.all;

entity Decoder2x4TB is
end Decoder2x4TB;

architecture Behavioral of Decoder2x4TB is

component Decoder2x4 is
port (i :in std_logic_vector(1 downto 0);
      e :in std_logic;
      o :out std_logic_vector(3 downto 0));
end component;


signal i:std_logic_vector(1 downto 0);
signal e :std_logic;
signal o :std_logic_vector(3 downto 0);

begin

inst:Decoder2x4 port map(i,e,o);
      
process

begin

    
    e<=transport '1' ;
    wait for 20 ns; 
    
    i<=transport "00" ;
    wait for 20 ns; 
    
    i<=transport "01" ;
    wait for 20 ns;
    
    i<=transport "10";
    wait for 20 ns;
    
    i<=transport "11";
    wait for 20 ns;
    
    
end process;

end Behavioral;